1. Field of the Invention
The present invention relates to a memory control circuit and a data rewriting method, which can reduce processing time for rewriting data stored in a storage element.
2. Description of Related Art
Hitherto, the following technique has been used for rewriting data stored in a memory or other such storage elements. FIG. 9 is a flowchart of a rewriting processing flow of the related art. Referring to FIG. 9, the related art is described below. According to the related art, if a CPU requests a memory control circuit to rewrite data, verification processing and retry processing (S800) are executed following write processing (S700).
To begin with, write data output from a CPU is written to a storage element in accordance with write processing in S700. Next, the data written to the storage element is compared with the original write data in S800 to determine whether or not the data is correctly written (verification processing). In the following description, data to write in the storage element is referred to as “write data”. Data obtained by reading the data written to the storage element for verification processing is referred to as “read data”. If the read data matches with the write data, and the data is correctly written, data rewriting processing is completed. If the read data does not match with the write data, and the data is not correctly written, processing of rewriting write data to mismatched data that has been written to the storage element (retry processing) is performed.
The processing of FIG. 9 is described below in more detail. FIG. 10 is a detailed flowchart of the write processing (S700) of FIG. 9. Referring to FIG. 10, operations in the write processing are described next. Although not shown, the memory control circuit of the related art includes a first memory storing write data output from the CPU and a second memory used for data transmission between the CPU and the first memory. First, if the CPU requests the memory control circuit to perform data rewriting processing, the memory control circuit is set to a write mode (S701). In S702, information about an address of the first memory to which the write data is written is acquired. As a unit processing amount of the write data, an area designated as a write target (hereinafter referred to as “designated area”) may be all processed, or the designated area may be divided in predetermined units to process each divided area. Incidentally, in the first memory, one address corresponds to one writing operation. In S703, write data is stored in the second memory. In S704, the write data is stored at the address of the first memory acquired in S702 (write control processing). In S705, it is determined whether or not data has been written to all the designated area. If the data has been written, the write processing is terminated. If the data has not yet been written, information about an address to which the next write data is written is retrieved (S706), and the next write data is stored in the second memory (S707). Then, the step S704 and subsequent steps are repeated.
FIG. 11 is a detailed flowchart of the verification processing and retry processing (S800) of FIG. 9. Referring to FIG. 11, operations in the verification/retry processing of the related art are described next. First, a verification mode is set in S801 to verify whether or not the data is correctly written to the first memory in the write processing (S700). In S802, information about an address of the first memory storing data to verify is acquired. In S803, write data corresponding to the data stored at the address retrieved in S802 is stored in the second memory. Upon verification control processing in S804, the data stored at the address of the first memory retrieved in S802 is read (read data) and compared with write data stored in the second memory. It is determined whether or not the write data matches with the read data (S805). If matched, whether or not the data written to the designated area has been all verified is determined (S806). If not all verified, address information for the next data to verify is acquired (S807). Then, write data corresponding to the data is stored in the second memory (S808), and the step S804 and subsequent steps are repeated.
In S805, if the write data does not match with the read data, that is, the write data is unverified, retry processing is performed from S809 forward. First, in S809, the memory control circuit is set to the write mode again. Next, write data corresponding to the data unverified in the write control processing is written to an address of the first memory (S810). In the second write control processing during the retry processing, the data stored in the first memory is referred to as “recorrection data”. The verification mode is set in S811, and recorrection data is read upon verification control processing in S812 and compared with corresponding write data. In S813, it is determined whether or not the write data matches with the recorrection data. If matched, an address for the next data to verify (verification data) is retrieved (S814). Then, write data corresponding to the verification data is stored in the second memory (S815), and the step S804 and subsequent steps are repeated. In S813, if the write data does not match with the recorrection data, retry processing is repeated plural times in S816. If the retry processing is normally completed before repeated a predetermined number of times, the procedure restarts with the step S809. If the data is unverified even after a predetermined number of retry processings are performed, the procedure is abnormally terminated.
Incidentally, another data rewriting technique is disclosed in Japanese Unexamined Patent Application Publication No. 2003-256266 (Maruyama et al.). According to the technique of Maruyama et al., at the time of writing data to a first memory, the data is written to a second memory and compared with data in the first memory, and then written to the first memory only if the comparison result is negative to thereby reduce unnecessary writing operations and save writing time. Further, the publication of Maruyama et al. describes a technique of comparing write data and read data divided into a predetermined size, and setting a mismatch flag if any of the divided data are not matched. Only the data with the mismatch flag is written to the first memory to reduce unnecessary writing operations.
However, the inventors of the subject application have found the following problems in the related art. In the verification processing of the related art, if verification ends in failure, retry processing for unverified data is immediately executed, and the procedure returns to verification processing after the retry processing. Upon the retry processing, the write processing and the verification processing are executed, so the memory control circuit should be switched between a write mode and a verification mode. Hence, each time data is unverified, the memory control circuit is switched between the write mode and the verification mode. A setup period for stabilizing a mode is necessary for switching the mode between a write mode and a verification mode. As a result, it is necessary to set aside some time for switching between a write mode and a verification mode each time data is unverified, so a data rewriting processing speed lowers. In particular, if plural data are unverified, a processing speed is remarkably lowered.
Further, although the technique of Maruyama et al. can reduce unnecessary writing operations by use of the mismatch flag, it is impossible to store data about which address in unit data obtained by dividing the original data into a predetermined size is mismatched. Thus, it is necessary to write the mismatched address to the first memory each time comparison is completed. That is, it is necessary to read data from the first memory and compare the read data with write data, and then write a mismatch flag to the first memory if the write data and the read data do not match. For example, in the case of writing a mismatched address to a storage element switchable between a writing operation and a reading operation such as a flash memory, a predetermined period is necessary for switching a mode for the writing operation or to generate an internal voltage. This leads to a problem that overhead time except actual write time is increased as the number of switching operations increases, and the whole write time is increased.